The present invention relates to apparatus and methods for providing an output signal proportional to the root-mean-square (RMS) value of an input signal. More particularly, the present invention relates to apparatus and methods for detecting an output fault condition and for recovering from such a condition so that an output signal is provided. The output signal may be a direct current (DC) signal proportional to the RMS value of an input signal (commonly called RMS-to-DC conversion).
The RMS value of a waveform is a measure of the heating potential of that waveform. RMS measurements allow the magnitudes of all types of voltage (or current) waveforms to be compared to one another. Thus, for example, applying an alternating current (AC) waveform having a value of 1 volt RMS gain stage 36. Gain stage 36 has an output VOUT, and provides a broadband gain A.
To simplify the description of pulse modulator 32 and demodulator 34, the following discussion first assumes that A=B=1 (although in practice it is common for A=B greater than 1). As described below, this assumption only affects a scale factor in the resulting analysis. Pulse modulator 32 may be any commonly known pulse modulator, such as a pulse code modulator, pulse width modulator, or other similar modulator. As shown in FIG. 1, pulse modulator 32 is implemented as a single-bit oversampling xcex94xcexa3 pulse code modulator, and includes integrator 40, comparator 41, switch 42, non-inverting buffer 44, and inverting buffer 46. As described in more detail below, switch 42 and buffers 44 and 46 form a single-bit multiplying digital-to-analog converter (MDAC) 47.
Integrator 40 has a first input coupled to input VIN, a second input coupled to the pole of switch 42, and an output coupled to an input of comparator 41. Comparator 41 has a clock input coupled to clock signal CLK, and an output V1 coupled to control terminals of switches 42 and 52. Clock CLK is a fixed period clock that has a frequency that is much higher than the frequency of input VIN (e.g., 100 times greater). Comparator 41 compares the signal at the output of integrator 40 to a reference level (e.g., GROUND), and latches the comparison result as output signal V1 on an edge of clock CLK.
Non-inverting buffer 44 provides unity gain (i.e., +1.0) and has an input coupled to the output of gain stage 38, and an output coupled to the first terminal of switch 42. Inverting buffer 46 provides across a resistor produces the same amount of heat as applying 1 volt DC voltage across the resistor.
Mathematically, the RMS value of a signal V is defined as:                               V          rms                =                                            V              2                        _                                              (        1        )            
which involves squaring the signal V, computing the average value (represented by the overbar in equation (1)), and then determining the square root of the result.
Various previously known conversion techniques have been used to measure RMS values. One previously known conversion system uses oversampling analog-to-digital converters to generate precise digital representations of an applied signal. The digital representations are demodulated and filtered to produce a DC output signal that has the same heat potential as the applied signal. This type of system is attractive to circuit designers because it produces highly accurate results and can be efficiently implemented on an integrated circuit.
FIG. 1 is a generalized schematic representation of a portion of an RMS-to-DC converter circuit. As shown in FIG. 1, RMS-to-DC converter circuit 30 includes pulse modulator 32, demodulator 34, gain stage 36, gain stage 38, and lowpass filter 54. Pulse modulator 32 has a first input coupled to VIN, a second input coupled to the output of gain stage 38 and an output V1. Demodulator 34 has an input coupled to VIN, a control input coupled to V1, and an output V2. Gain stage 38 has an input coupled to VOUT, and provides a broadband gain B. Lowpass filter 54 has an input coupled to V2 and an output V3 coupled to the input of inverting gain (i.e., xe2x88x921.0) and has an input coupled to the output of gain stage 38, and an output coupled to the second terminal of switch 42.
V1 is a signal having a binary output level (e.g., xe2x88x921 or +1). If V1=+1, the pole of switch 42 is coupled to the output of non-inverting buffer 44. That is, (assuming gain B=1)+VOUT is coupled to the second input of integrator 40. Alternatively, if V1=xe2x88x921, the pole of switch 42 is coupled to the output of inverting buffer 46. That is, (assuming gain B=1)xe2x88x92VOUT is coupled to the second input of integrator 40. This switching configuration provides negative feedback in pulse modulator 32.
The first and second inputs of integrator 40 therefore can have values equal to:
xe2x88x92VOUTxe2x89xa6VINxe2x89xa6+VOUTxe2x80x83xe2x80x83(2)
and VIN thus has a bipolar input signal range.
From equation (2), if V1 has a duty ratio D between 0-100%, D can be expressed as:                               D          =                                    1              2                        xc3x97                          (                                                                    V                    IN                                                        V                    OUT                                                  +                1                            )                                      ,                  0          ≤          D          ≤          1                                    (        3        )            
That is, if VINxe2x88x92VOUT, D=0, and if VIN=+VOUT, D=1.
Demodulator 34 includes non-inverting buffer 48, inverting buffer 50 and switch 52, which form a single-bit MDAC. Non-inverting buffer 48 has an input coupled to VIN, and an output coupled to a first terminal of switch 52. Inverting buffer 50 has an input coupled to VIN, and an output coupled to a second terminal of switch 52. Switch 52 has a control terminal coupled to V1 and a pole coupled to the input of lowpass filter 54.
If V1=+1, the pole of switch 52 is coupled to the output of non-inverting buffer 48. That is, +VIN is coupled to the input of lowpass filter 54. Alternatively, if V1=xe2x88x921, the pole of switch 52 is coupled to the output of inverting buffer 50. That is, xe2x88x92VIN is coupled to the input of lowpass filter 54.
Demodulator 34 provides an output signal V2 at the pole of switch 52 that may be expressed as:                               V          2                =                  xe2x80x83                ⁢                                            +                              V                IN                                      xc3x97            D                    -                                    (                              -                                  V                  IN                                            )                        xc3x97                          (                              D                -                1                            )                                                                    xe2x80x83                ⁢                  (                      4            ⁢            a                    )                                        =                  xe2x80x83                ⁢                              V            IN                    xc3x97                      (                                          2                xc3x97                D                            -              1                        )                                                        xe2x80x83                ⁢                  (                      4            ⁢            b                    )                    
Substituting equation (3) into equation (4b), V2 is given by:                               V          2                =                              V            IN            2                                V            OUT                                              (        5        )            
Lowpass filter 54 may be a continuous-time or a discrete-time filter, and provides an output V3 equal to the time average of input V2. Accordingly, V3 equals:                               V          3                =                                            V              IN              2                        _                                V            OUT                                              (        6        )            
Gain stage 36 provides an output VOUT equal to (assuming gain A=1) V3:                               V          OUT                =                  xe2x80x83                ⁢                                            V              IN              2                        _                                V            OUT                                                        xe2x80x83                ⁢                  (                      7            ⁢            a                    )                                        =                  xe2x80x83                ⁢                                                            V                IN                2                            _                                =                      V            RMS                                                        xe2x80x83                ⁢                  (                      7            ⁢            b                    )                    
Thus, circuit 30 has a bipolar input range and provides an output VOUT equal to the RMS value of input VIN.
Demodulator 34 and stage 47 each are single-bit MDACs and comparator 41 is a single-bit analog-to-digital converter (ADC) that provides a single-bit output V1. The difference between the output of integrator 40 and MDAC 47 equals the quantization error e[i] of pulse modulator 32.
Because the output of comparator 41 controls the polarity of the feedback signal from VOUT to the input integrator 40, converter 30 will remain stable for only one polarity of VOUT. If VOUT has a polarity opposite of that assumed for the connection of switch 42 (e.g., during power up, a brown out, or a load fault), modulator 32 will become unstable, and the output of integrator 40 will quickly approach a rail voltage.
With a DC input, this may not be problematic, because the state of V1 might be such that VIN propagates through MDAC 34 and results in the V2 polarity desired for VOUT. In this case, once any external influences on VOUT are removed, V2 (and therefore VOUT), will return to the proper polarity once it propagates through low pass filter 54. This sequence, however, has a probability of occurring only about 50% of the time, meaning that converter 30 is unlikely to recover in almost half of the possible DC operating cases. Moreover, RMS-to-DC converters are most often used with AC signals, and in those instances output recovery is even less likely to occur.
Thus, in view of the foregoing, it would be desirable to provide methods and apparatus for performing RMS-to-DC conversions that have improved recovery characteristics.
Accordingly, it is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversions that have fault detection and recovery capabilities.
In accordance with this and other objects of the present invention, circuitry and methods that supply the root-mean-square (RMS) value of an input signal and that detect and independently recover from output fault conditions are provided. The circuit of the present invention includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit of the present invention generates a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to the RMS mode of operation.